1. Field of the Invention
This invention is related to a packaging structure of semiconductor elements and, more particularly, to a packaging structure for high yield packaging of semiconductor elements on which pads are formed with high density.
Semiconductor elements currently being mounted on a PC board are required to be compact and light in weight and, moreover, they are required to be driven at a high frequency. Accordingly, downsizing of the board itself is required and the high-density packaging of semiconductor elements is required.
2. Description of the Related Art
FIGS. 5(a)-5(c) show a prior art structure for mounting semiconductor elements onto a board at high density. FIG. 5(a) shows the mounting of an SOP package of semiconductor elements; FIG. 5(b) shows the mounting of a PGA package of semiconductor elements; and FIG. 5(c) shows the mounting of a BGA package of semiconductor elements. Furthermore, corresponding numbers in these figures indicate components which have the same function.
SOP package 1, as shown in FIG. 5(a), is connected to footprint 4 provided on a board through a lead extending outwardly from a package by soldering. SOP package 1 is a compact package of semiconductor elements mounted on the surface of a board, where the lead wire 2 is very thin and the space between the leads is extremely narrow. As a result, the space between the footprint 4 corresponding to the lead wire 2 must also be narrow, so the footprint must have a rectangular shape, as shown in the figure. The solder used in mounting SOP package 1 is a solder paste and is supplied by screen printing. In order to make screen printing smooth, there is a case using a structure in which the corners of footprint may be chamfered. Furthermore, in the SOP package 1 shown in FIG. 5(a), since lead wires on the SOP package 1 could not be completely arranged, there is a QFP package having leads all around a package.
Conversely, where a number of terminals cannot be ensured only around the package such as SOP, QFP, or where the density of terminals cannot be increased due to terminal connections with sockets, there is known a PGA package in which the terminals are arranged in two or more rows.
As shown in FIG. 5(b), PGA package 1 has pins 2 extending downward from the package, which are arranged in a matrix, and which are soldered to the footprint 4 provided on the board 3 corresponding to the pins 2. In this case, while it is possible to form the footprint 4 in a square shape where the density of pins is low, where the density of pin is high the footprint is formed in a circular shape.
There is also known a BGA package for more higher density packaging. Most BGAs are similar in size to silicon boards (hereinafter referred to as "bare chips") on which semiconductor element circuits are structured, and are used in so-called chip scale packages.
As shown in FIG. 5(c), BGA package 1 has terminals connected to aluminum electrodes formed on the bare chip along the entire bottom surface of the package, and solder balls 2 are formed on these terminals. The solder balls 2 of the BGA package 1 are connected to the footprint 4 by melting the solder ball 2 through heating the board 3 in a furnace after the solder balls 2 have been positioned and mounted on the round shape footprint 4 provided on the board 3.
All these prior art packages enable the easy mounting of semiconductor elements onto the board by extending lead wires from terminals of a bare chip and by connecting the lead wires to terminals which have a lower density than that of terminals of the bare chip. However, there is a method of mounting directly to the board 3 without converting the terminal density of the bare chips to a lower terminal density as described above.
FIGS. 6(a)-6(e) are diagrams for explaining a prior art packaging method which is a method of packaging a bare chip directly to a board called "facedown bonding" or "flip-chip bonding". FIGS. 7(a)-7(b) are diagrams showing pads on a bare chip and footprints on a board.
As shown in FIG. 6(a), bump 53 is formed on the pads 52 of a bare chip 51. When the end of the gold wire 55 provided at the end of the capillary 54 of the wire bonder is heated and melted, a ball 56 is formed by the surface tension of the gold. Then, when the ball 56 is crimped onto the pad 52, the ball 56 is fixed to the pad 52. Then, by moving the capillary up in the figure, the gold wire 55 is cut, and a bump 53 is formed. At this time, bump 53 is positioned at the center of the pad 52, as shown in FIG. 7(a). This insures that failure rarely occurs, even if the forming position of a bump shifts in any direction due to inaccurate positioning of a machinery or the tolerance of dimensional precision of the bare chip. Next, as shown in FIG. 6(b), the bare chip 51 is pressed to face a surface forming the bumps 53 to a glass 57. By pressing the bare chip 51 to the glass 57 whose surface is formed as flat, the cut-out gold wire 55 remaining at the end of the bump 53 is squashed, and then the heights of all bumps 53 are uniform. Next, if, as shown in FIG. 6(c), the bumps 53 dip to a surface thinly coated with conductive adhesive 58, the conductive adhesive 58 coats only the bumps 53. Next, as shown in FIG. 6(d), the bare chip 51 is positioned and pressed onto a board 59 by a mounting device called a flip-chip bonder. At this time, as shown in FIG. 7(b), an adhesive 61, which is made of thermosetting resin for securing the bare chip is coated in the center, which is a position of mounting the bare chip on the board 59, of the area surrounded by footprint 60, so the adhesive 61 is spread toward the periphery by pressing the bare chip 51 onto the board 59. As shown in FIG. 6(e), while the bare chip 51 is being pressed onto the board 59, the adhesive 61 is spread around the bare chip through the spaces between the bump 53. Then, due to the surface tension of the adhesive 61, a fillet 61', which covers the sides of the bare chip, is formed. By then heating the board in a furnace in this state, the adhesive 61 hardens and the bare chip is mounted.
All footprints used in packages such as the SOP, PGA, BGA, etc., as described above, are formed in a manner such that the width of the footprints is greater than the wiring patterns formed on the boards. The incomplete forming of footprints does not adversely affect the production yield of the boards. However, when using packages, it is difficult to increase the packaging density, to reduce weight, or to improve thermal radiation efficiency. For example, there is a requirement to mount bare chips on the boards even in portable personal computers. For the flip-chip mounting of bare chips with a high terminal density, however, it is typical to use boards manufactured by using thin film technology. From this, the footprints used to mount bare chips are formed in a manner such that the width of each footprint is greater than the diameter of each of the wires formed on a board, as described above. However, because the production yield of boards using thin film technology is low, such boards cannot be manufactured at a low enough cost to be used in low-priced consumer products such as personal computers.
Multi-layered boards manufactured with thick-film technology are formed in a manner such that a plurality of double-sided boards containing a copper pattern having a thickness of about 20 .mu.m are adhered to one another, and thereafter the through-holes are formed by plating. In this case, each copper pattern formed on the surface has a thickness of about 40 .mu.m. Consequently, it is necessary that the width of wiring pattern and the spaces between patterns are respectively 150 .mu.m, therefore, patterns with a pitch of at minimum 300 .mu.m can be formed. To solve this problem, a built-up board forming a printed circuit by thick-film is provided in a manner such that insulated polyimide film and copper film are layered on these boards to be used as a core, and then the copper film is etched. By using this built-up board, it is possible to form more minute wiring patterns. However, even if such a built-up board is used, the thickness of the wiring patterns is still about 10 to 15 .mu.m, and because 50 .mu.m is required both for the width of each wiring pattern and for the spaces between the patterns, it is only possible to form a pattern with a pitch of 100 .mu.m.
Conversely, because the gaps between pads of bare chips are defined and manufactured by a chip maker, custom chips having a specific wiring density for each type of board cannot be manufactured. For example, a Pentium.RTM. bare chip of Intel Corporation has a pad space of 85 .mu.m and, in order to mount this bare chip, footprints with a space narrower than the manufacturing limit of conventional wiring on built-up boards must be formed.
Therefore, assuming that a footprint width of 50 .mu.m is the manufacturing limit, the clearance between the footprints is at maximum only 35 .mu.m, and consequently, many faulty boards with insufficient insulation are manufactured, resulting in a poor production yield. In order to improve the manufacturing precision of boards, if plating and etching solutions are strictly controlled, these solutions must be replaced every time and the production costs become extremely high. Furthermore, because only those solutions with a limited pH value can be used, production costs are yet further increased. Moreover, if these solutions are replaced every time, the subsequent heating to the specified temperatures takes a long time, thereby limiting the number of products manufactured daily and resulting in increased costs.
If the width of each of the footprints is 35 .mu.m, the number of insulation failures can be reduced and the production yield of boards can be improved, but the footprint areas are reduced. For this reason, when a bare chip is mounted, the mounting position tends to shift slightly or a slight position shift during bump forming causes conduction failure between the bare chip and the board. As a result, manufacturing defects are likely to occur at the packaging stage and such manufacturing defects in finished products whose price is higher than the unit price of boards result in increasing the overall cost. In order to avoid such disadvantages, such manufacturing defects could be reduced in number by doing a visual check of the external appearance of bumps during their formation, and removing bare chips with even slightly shifted bumps as being faulty. However, this adds a process of visually inspecting bumps, and the failure rate of bare chips increases, resulting in increased costs. Furthermore, by narrowing the widths of footprints, the areas of footprints are reduced and the adhesive strength between copper foil and polyamide used as the insulation layer is weakened. Consequently, the increased number of defects, such as peeled-off copper foil forming footprints when pressing a bare chip onto a board, increases production costs.
By taking a middle ground between these cases, by forming footprints each 40 .mu.m wide and visually checking them and discarding faulty boards having footprints each less than 40 .mu.m wide, the production cost is kept low. However, because of the addition of the process of inspecting footprint appearance and where only one of a plurality of footprints on a board is defective the board is considered to be faulty, the production yield of boards can hardly be expected to improve.
Because the spaces between pads on a bare chip is narrow, the spaces between bumps formed on pads are also narrow, and the productivity of products on which bare chips are mounted is adversely affected.